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[Windows Develop] ram

Description: verilog写双端口存储器模型-a Model of Writing Double-Port RAM developed with Verilog
Platform: | Size: 1067 | Author: 杨艳 | Hits:

[Other resource] fifo-ram

Description: 采用Verilog语言描述的FIFO和双端口RAM源代码。
Platform: | Size: 762 | Author: 蒋大为 | Hits:

[Other resource] ram

Description: RAM， Random-access memory，Verilog code
Platform: | Size: 14745 | Author: leigh lee | Hits:

[Other resource] Synchronous_read_write_RAM

Description: Synchronous read write RAM verilog。经过modelsim se仿真。
Platform: | Size: 1104 | Author: lianlianmao | Hits:

[Other] ram_sp_sr_sw

Description: Synchronous read write RAM verilog
Platform: | Size: 965 | Author: 李明 | Hits:

[Other] verilog编写的ram

Description: verilog编写的ram
Platform: | Size: 1361 | Author: yanshaner | Hits:

[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[Other] verilog_fifo

Description: verilog fifo
Platform: | Size: 4096 | Author: 王新 | Hits:

[Special Effects] videofram

Description: 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image frame buffer cards logical verilog procedures, Quartus II 5.0 Open
Platform: | Size: 1024 | Author: 陈刚峰 | Hits:

[Other] proposal

Description: 某个著名博士关于如何查找文献，和学术论文发表的ppt-a famous literature on how to identify and academic papers published ppt
Platform: | Size: 35840 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] sdr_c_trl_verilog

Description: SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
Platform: | Size: 12288 | Author: 曹大壮 | Hits:

[VHDL-FPGA-Verilog] DDS_Power

Description: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Platform: | Size: 16384 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] Sobel--Image_Filter_An_Image_filtering_VHDL

Description: Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip-Sobel-- Image Filter (I). An Image filteri Vi is made over the data loaded into RAM on board a nd presented on a VGA monitor.zip
Platform: | Size: 316416 | Author: 严刚 | Hits:

[Streaming Mpeg4] bit_intealeaver1

Description: verilog HDL语言实现dvb_t中的比特交织器源代码描述-verilog HDL language dvb_t the bit interleaver source code Description
Platform: | Size: 1024 | Author: wenjuner | Hits:

[VHDL-FPGA-Verilog] DULE-RAM

Description: 基于VERILOG的双口ram例子，比较简单，不是很复杂，入门了解就可以了。-Based on dual port ram VERILOG example, the relatively simple, not very complicated, entry understand it.
Platform: | Size: 101376 | Author: 张是非 | Hits:

[VHDL-FPGA-Verilog] basic verilog codes

Description: Basic Verilog code includes RING and Johnson counters, Up-down counters, RAM, ROM, SIPO, PISO, SISO, PIPO, Mealy and Moore FSM codes
Platform: | Size: 9386 | Author: spgp1306 | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

[VHDL-FPGA-Verilog] verilog实例 [43项]

Description: 一些采用verilog描述的数字功能模块，有常见的同步异步FIFO，RAM等模块，适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
Platform: | Size: 190464 | Author: hayto | Hits:
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